Defects (e.g. particles) can cause electrically measurable faults (killer defects) dependent on the chip layout and the defect size. These faults are responsible for manufacturing related malfunction of chips. So, defect density and size distributions are important for yield enhancement and to control quality of process steps and product chips, as described in Staper, C. H., Rosner, R. J., “hirtegrated Circuit Yield Management and Yield Analysis: Development and Implementation,” IEEE Transactions on Semiconductor Manufacturing, pp. 95–102, Vol. 8, No. 2, 1995.
Test structures are used to detect faults and to identify and localize defects. The double bridge test structure was proposed by Khare, et al., “Extraction of Defect Size Distributions in an IC Layer Using Test Structure Data,” IEEE Transactions on Semiconductor Manufacturing, pp. 354–368, Vol. 7, No. 3, 1994, to extract size distributions based on electrical measurements.
Parallel lines—each connected to two pads—are implemented inside a test structure to electrically determine a defect size distribution. If a defect occurs and causes an electrically measurable fault, either two or more test structure lines are shorted or one or more test structure lines are opened. The greater the number of test structure lines involved, the larger the defect that caused this measured fault.
The principle prior art test structure of nested serpentine lines is based on a structure proposed by Glang, R., Defect Size Distribution in VLSI Chips, “IEEE Transactions on Semiconductor Manufacturing,” pp. 265–269, Vol. 4, No. 4, 1991.
Glang used 5 serpentine lines within two combs, and implemented several structures having different dimensions to determine a defect size distribution by comparing the number of detected defects dependent on the dimension of the structures. Having a high number of nested serpentine lines enables the direct extraction of defect size distribution by comparing the number of detected defects dependent on the number of involved lines.
Each NEST structure is connected to a 2-by-N pad frame. In a 2-by-N pad frame, to enable the detection of opens and shorts, each test structure line is connected to two pads. So, only N/2 lines are implemented; that does not fill a relatively large chip area that is sufficient to detect random defects. For this reason, the lines are designed as serpentines to fill the complete test chip area. Thus, each line is divided into a plurality of segments between serpentine turns. The prior art structures do not provide a satisfactory method to isolate the location of a defect within a given line having a plurality of serpentine segments.